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In the race to produce ever-faster chips, it sometimes feels like enough is enough. Our desktops have sufficient horsepower to simulate the birth of galaxies if anyone wants to. Phones and PDAs are stuffed with fascinating communications tricks that few people will ever use. So do we still need Moore's Law -- the precept that chip performance should double roughly every 18 months?
The electronics industry says yes, for reasons of cost and capability. There are still a few billion people on the planet who have yet to purchase a cell phone, let alone a PC. So if chipmakers can keep Moore's Law on track for a few more years, the digital amenities that rich countries take for granted will be cheap enough for everyone to buy, brainy enough to understand requests in natural spoken language, and even to answer back.
Now more than ever, though, upholding Moore's Law will require imagination. So far chip companies have relied mostly on one clever trick: They shrink the transistors on chips so that electrons have less distance to travel, thereby speeding up the processing of data. But that trick is getting harder to perform. In the 1990s, shrinking led reliably to faster speeds. It was "the cream-puff era," says Gary Smith, chief analyst at Gartner Dataquest (IT
) in San Jose, Calif. Today, though, circuits are packed so closely that chips are heating up, and performance is starting to suffer. That's one reason giants such as Intel Corp., No. 52 on this year's Info Tech 100, and IBM, No. 44, have fallen behind schedule in launching new generations of microprocessors in recent years.
Even so, chipmakers think they can still pull off a few more generations of shrinking before they hit the wall. They're trying new materials and production tools, and most experts see an orderly progression deep into nanotechnology. Today's circuit lines measure about 90 nanometers in width -- or 90 billionths of a meter. This year and next they'll go down to 65 nm, then 45 nm by 2010, 32 nm by 2013, and 22 nm by 2016, says International Technology Roadmap for Semiconductors, an industry research group. After that, says Paolo A. Gargini, Intel's director for technology strategy, "it's unclear what will come next."
Fortunately, shrinking is just one way to solve the problem. Another strategy that is already moving into the marketplace involves linking several microprocessor "cores" together on the same semiconductor. This will require overhauling the software running on the chip. In addition, engineers are devising new ways to stack circuitry, layer upon layer, into multi-story, 3D structures. Together, these developments should sustain momentum in the $227 billion global chip sector for years, if not decades. They could even lead to a quantum leap in performance. "We're going to see a lot of evolution happening very fast," says IBM's Philip Emma, manager of systems technology and microarchitecture.
Among these different approaches, the first superfast chips coming out of the gate are the multicore devices that boost performance by replacing a single high-speed processor with two or more cores that don't need to be so speedy. "A 300-pound lineman can generate a lot of power," says IBM's Emma. "But two 160- pound guys can do the same work with less overall effort." On your desktop, this means replacing a single 3 gigahertz chip with two 2.1 GHz cores. Combined, they can move data faster using less energy while running cooler.
Already being sold by Advanced Micro Devices (AMD
), IBM, and Intel for use in desktop PCs, multicore processors have another advantage: Their behavior is well understood. For decades companies have built supercomputers that function on this principle, with packs of processors working together to raise computing speeds. Still, there's a world of difference between these two segments of the market. IBM's world-beating Blue Gene/L supercomputer boasts 65,000 processors working in unison. In contrast, microprocessors in personal computers are likely to peak at around eight cores, predicts Emma.Chip Skyscrapers
A more radical reinvention of chips is on drawing boards. Three-dimensional, or stacked, semiconductors promise dramatic performance gains simply by arranging chip functions vertically -- like the floors of a building. Consumer-electronics makers have already taken a step in this direction, notes Hans Stork, chief technology officer at Texas Instruments Inc., No. 66, in Dallas. In portable devices such as phones and PDAs, where real estate is limited, individual chips often are stacked on top of one another, separated by circuit boards and connected by millimeter-long wires.
Why should stacking chips in this fashion increase speed and reduce power consumption? James Jian Qiang Lu of Rensselaer Polytechnic Institute in Troy, N.Y., explains it this way: If you slice a one-cm square processor into four pieces and directly connect critical functions in a stack, you can cut the maximum distance that electrons have to travel from 20,000 microns to as little as 10. The shorter path ramps up speed and also means that less power is needed to keep the electrons flowing, which in turn lowers heat output. Lu figures that by stacking the elements of one of today's two-dimensional, 90-nm chips you could achieve computing speeds comparable to the 32-nm chips that are set to arrive in about six years.
Still, it may take that long for all the technical hurdles confronting 3D chips to be resolved. Just as constructing a skyscraper is harder than building a house, creating 3D chips will require the development of complex 3D design tools and methods. Lu's research group is focusing on the assembly process, which will also be much more complicated. To glue one chip layer to another means removing the tough structural base material to expose the chip's underside, then lining it up and attaching the layers so that micron-sized contacts touch.
The physical reorganization of chip architecture will force a similar upheaval in the software world. Multicore designs work most efficiently when software can chop up a task and divide it into batches of work that can be processed simultaneously, in parallel. Unfortunately, little of today's software is optimized for this, whether it's the programs embedded on the chip itself or the word processor on your desktop. Once optimized, however, software performance can improve dramatically, says Shahrokh Daijavad, software lead for next-generation computing systems at IBM. That's especially true of media and gaming software, he notes.
But converting all that software is bound to take years. Developing software for multicore processing "is one of the hardest things you learn in computer science," says Daijavad. Seeing the challenge, Intel has committed 3,000 of its 10,000 software programmers to help accelerate the shift to multicore designs.
For all the handwringing over the demands of Moore's Law, chipmakers say they have faced this abyss before and survived. Last year, when the industry moved from 130-nm to 90-nm lines, there were wrenching interruptions in chip deliveries. But in this case, as in every setback since 1965, when Gordon E. Moore first penned his famous law, the industry has found a way around the roadblocks. Even the now-retired Moore concedes that he's consistently impressed by the industry's ability to keep moving ahead. Some of the new tricks emerging today are bound to deliver gains that will impress Moore yet again. By Adam Aston