Posted by: Ihlwan Moon on September 11, 2006
Korea’s Samsung Electronics on Sept. 11 unveiled a new semiconductor using technology that the company says makes it possible to double the capacity of flash memory chips every year. The new 32-gigabit (Gb) NAND is the first chip to apply so-called Charge Trap Flash (CTF) architecture, a technology enabling chipmakers to print circuits in lines 1/3000 the width of a human hair.
Samsung President Hwang Chang Gyu says the memory chip industry has had difficulty trimming lines on the most advanced chips beyond 50 nanometers, but CTF allowed his company to push it to 40 nm. CTF means Samsung can further trim circuit lines to 20 nm within a couple of years, he says. Using thinner processing technology means individual chips can shrink. In other words, more can be cut from each wafer, pushing chip costs lower.
Hwang says the CTF architecture, replacing the conventional Floating Gate architecture, increases the reliability of flash chips by sharply reducing inter-cell noise levels. It also reduces chip processing steps by 20%, which will cut costs further. The mass production of the 32-Gb chip enables the marketing of a 64-gigabyte memory card, or enough room to hold about 40 movies.